Field
Circuit devices and the manufacture and structure of fin based circuit devices.
Description of Related Art
Increased performance in circuit devices on a substrate (e.g., integrated circuit (IC) transistors, resistors, capacitors, etc. on a semiconductor (e.g., silicon) substrate) is typically a major factor considered during design, manufacture, and operation of those devices. For example, during design and manufacture or forming of metal oxide semiconductor (MOS) transistor devices, such as those used in a complementary metal oxide semiconductor (CMOS), it is often desired to increase movement of electrons in N-type MOS device (n-MOS) channels and to increase movement of positive charged holes in P-type MOS device (p-MOS) channels. However, performance and movement are slowed by lattice mismatches and defects generated in a between layers of materials used to form the MOS.
For some CMOS implementation, the co-integration of lattice mismatched materials like III-V material epitaxial growth on Silicon is a big challenge. Currently there is no state of art solution to co-integrate n- and p-MOS material epitaxial growths on to a single Silicon substrate. Thus, in current applications, due to large lattice mismatch in materials, defects are generated when novel materials (III-V, Germanium (Ge)) are grown on a Silicon material substrate. These applications also fail to provide an efficient and reliable process for forming both p- and n-type epitaxial electronic device fins from the same substrate.